Field of the Invention
The present invention relates to a method of manufacturing a solid-state image sensor.
Description of the Related Art
Along with an increase in the number of pixels of a solid-state image sensor, fineness is required not only for a photoelectric conversion element but also for MOS transistors arranged in a pixel area and a peripheral circuit area. If the photoelectric conversion element and elements such as MOS transistors or the like are fined, the fineness of an active region where the elements are formed and an element isolation which isolates the active region is also required accordingly. An STI (Shallow Trench Isolation) is advantageous for a minute element isolation.
A layout is desired, which increases an area ratio made up by the photoelectric conversion element to ensure the sensitivity of the photoelectric conversion element even if the fineness of the pixels advances. Under such a requirement, a ratio occupied by the active region tends to be high, as compared with the peripheral circuit area, in the pixel area where a number of photoelectric conversion elements are arranged as periodic patterns. The difference of the occupancy ratio of the active region between the pixel area and the peripheral circuit area may have an influence on a planarizing process of eliminating a step between the active region and the element isolation. More specifically, the amount that the element isolation protrudes above the reference surface of the active region can be larger in the pixel area than in the peripheral circuit area. Note that the amount (height) that the element isolation protrudes above the reference surface of the active region is defined as a protrusion amount.
There is known a method called pre-etch which removes, before planarizing an insulating film where a trench for the element isolation is buried, a part of the insulating film in the active region by etching in order to reduce the difference of the protrusion amount between the pixel area and the peripheral circuit area. Adding this pre-etching process makes it possible to reduce the step after planarization even if the patterns having a different area occupancy ratio between the active region and the element isolation are mixed with each other.
Furthermore, there is proposed a technique of reducing the difference of the protrusion amount after planarization between the pixel area and the peripheral circuit area by making the distance between the end of the element isolation and the end of an opening formed on the active region by pre-etch smaller in the pixel area than in the peripheral circuit area (refer to Japanese Patent Laid-Open No. 2009-117681).
However, as the fineness of the pixels advances, the dimension of the active region in the pixel area decreases accordingly. If the dimension of the active region in the pixel area decreases, patterning of the insulating film on the active region by pre-etch becomes difficult. Even if patterning by pre-etch is possible, a method of controlling the distance between the end of the element isolation and the end of the opening formed by pre-etch has its limits. For example, if even a portion that should be left as the element isolation is etched by pre-etch, undesirable leakage may occur in the element isolation. It is therefore necessary to determine a rule of determining the positional relationship between a pre-etch pattern (opening pattern) and the active region in consideration of constraints such as variations in a processing dimension and a positional shift in pattern formation. As described above, if the fineness of the pixels advances, more constraints are imposed on the arrangement of the pre-etch pattern. This makes it difficult to sufficiently reduce the difference of the protrusion amount of the element isolations between the pixel area and the peripheral circuit area after planarization.
A problem caused when the protrusion amount becomes larger in the pixel area than in the peripheral circuit area is that an etching residue in an etching process of a gate electrode film may occur. The etching residue may occur especially in a portion where the step is large (that is, a boundary portion between the active region and the element isolation within the pixel area) before forming the gate electrode film.